Samsung, the world’s largest memory chip maker, is striving to catch up with rivals Taiwan Semiconductor Manufacturing Co. (TSMC) and SK hynix in the fast-growing AI chip market.
At the annual Samsung Foundry Forum in San Jose, California, on Wednesday (local time), the company announced an initiative to enhance its one-stop service for AI chip production, encompassing development, contract manufacturing and packaging.
"Alongside our proven GAA (gate-all-around) process optimized for AI chips, we plan to introduce integrated, co-packaged optics (CPO) technology for high-speed, low-power data processing, providing our customers with the one-stop AI solutions they need to thrive in this transformative era," said Choi Si-young, head of Samsung's foundry business division.
The tech giant aims to apply backside power delivery network (BSPDN) technology to its 2-nanometer (nm) process "SF2Z." BSPDN improves bottlenecks in power and signal lines by placing power rails on the backside of the wafer. Currently, semiconductor power rails are drawn on the front side of the wafer.
Through BSPDN technology, Samsung expects to achieve improvements in power, performance and area compared to the existing 2-nanometer process, as well as significantly reduce voltage drop phenomena that destabilize current flow.
TSMC, the world's largest foundry firm, plans to introduce BSPDN technology to its 1.5-nanometer process by 2026.
Samsung also plans to integrate optical device technology, which enables high-speed data processing with low power consumption using light, into its AI solutions by 2027.
In 2025, Samsung will begin mass-producing chips using its optical shrink technology, which reduces chip size while enhancing performance, in its existing 4-nanometer process.
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