Samsung Electronics has broken through the integration limits of logic semiconductors using vertical stacking technology. By applying the stacking concept, previously used in memory semiconductors, to logic semiconductor transistors, the company has developed a new structure that increases integration density per unit area.
On June 17, Samsung announced that its semiconductor research institute had implemented the industry's smallest vertical stacking transistor, the 3D Stacked FET, at the VLSI Symposium held in the United States this month. The paper detailing this achievement was selected as the best paper at the 2026 VLSI Symposium.
The VLSI Symposium is recognized as one of the top three semiconductor conferences globally, alongside IEDM and ISSCC. It serves as a platform for semiconductor experts worldwide to present next-generation devices and process technologies. Samsung's achievement has garnered attention from both academia and industry as it proposes a new structure for logic semiconductors facing miniaturization limits.
The core of this technology lies in stacking transistors vertically rather than arranging them flat. Samsung has applied three nanosheet channels to each layer, widening the pathways for current flow. Additionally, the company developed an intermediate insulation layer to prevent electrical interference between the stacked transistors.
Historically, the semiconductor industry has enhanced performance by making transistors smaller. However, as the spacing between devices decreases, the insulation layers also thin, leading to increased electrical interference. It has become increasingly difficult to improve integration density through horizontal miniaturization alone.
Samsung has addressed this limitation through vertical stacking. By stacking transistors, more devices can fit into the same area, theoretically doubling the integration density per unit area. Similar to how NAND flash's V-NAND and DRAM's HBM have overcome area limitations through vertical stacking, logic semiconductors are now beginning to transition in the same direction.
The gate pitch has also been reduced. Prior to this announcement, the industry's smallest gate pitch was 48nm. Samsung's research team has lowered this to 42nm, setting a new standard. Gate pitch indicates the width of a single transistor; a smaller value allows for more transistors to fit in the same area.
Samsung believes this new structure is suitable for next-generation logic semiconductors designed for AI and high-performance computing (HPC). By applying vertical stacking, the number of transistors in the same area increases, improving power efficiency. Unlike the typical performance improvement of around 15% seen in transitions between existing process generations, vertical stacking theoretically has the potential to double performance.
Power efficiency is also crucial. AI semiconductors must handle more computations with lower power consumption. In a context where data center power demands are rising, a device structure that can improve both chip area and power efficiency could become a significant factor in the competition for next-generation logic semiconductors.
In a newsroom interview, Kwon Wook-hyun, Master of the Logic TD team at Samsung's semiconductor research institute, stated, "The 42nm gate pitch indicates the width of a single transistor. Before our paper was published, the industry's smallest size was 48nm, and our 42nm is the world's smallest transistor ever implemented in the industry."
The research team views this achievement as a starting point for actual product development. Kwon noted, "This research vertically stacked the n-type and p-type transistors, which are the fundamental units of logic products. To use a construction analogy, we have made the bricks." He added that they plan to continue research with actual circuit implementations, such as ring oscillators and SRAM.
Through this research, Samsung has suggested that the competitive landscape for logic semiconductors may shift from horizontal miniaturization to vertical stacking. As competition intensifies in AI semiconductors and HPC chips, the ability to achieve higher performance and power efficiency in smaller areas is emerging as a key technology in the race for next-generation processes.
* This article has been translated by AI.
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