The KAIST research team has developed next-generation memory technology that enhances the performance of AI semiconductors while reducing power consumption. This innovation addresses the persistent defect issues associated with the three-dimensional structure of stacked semiconductors.
On August 20, KAIST announced that a research team led by Professor Kwon Ji-min from the Department of Electrical Engineering, in collaboration with researchers from UNIST and Yonsei University, has developed a new multilayer interlayer insulating film structure that significantly reduces defects in oxide vertical channel transistors (VCT), improving performance and stability.
For decades, DRAM technology has evolved by shrinking device sizes to store more data in the same area while lowering power consumption. However, as the physical limits of continuously miniaturizing semiconductors in a planar manner are approached, three-dimensional structures that stack devices vertically are gaining attention.
The VCT is designed with a channel that conducts current vertically rather than horizontally, allowing for a higher density of devices in a limited area, which is advantageous for high-density memory implementation. Using oxide semiconductors for the channel material also significantly reduces current leakage.
A key challenge was the 'oxygen vacancy' phenomenon, where oxygen atoms are missing from the oxide semiconductor. An increase in these vacancies alters the electrical properties of the semiconductor, making stable operation difficult. However, simply supplying oxygen can lead to oxidation of the metal electrodes, negatively impacting performance. Therefore, precise control of oxygen movement was necessary.
To address this, the research team developed a new multilayer interlayer insulating film composed of silicon nitride, silicon dioxide, and silicon nitride (SiN·SiO₂·SiN). This insulating film serves not only as an electrical barrier but also as an 'oxygen tunnel' that allows oxygen to move toward the oxide semiconductor while restricting its movement toward the electrodes that should not oxidize.
As a result, the research team achieved world-class current flow and data retention times in the field of oxide VCTs. After applying over 10 million operational stress cycles to the device, the threshold voltage change remained below 50 millivolts (mV), confirming high operational stability. Additionally, the team implemented technology to combine existing silicon-based CMOS semiconductors with the new oxide semiconductors to evaluate system performance.
This technology is expected to enhance the performance of compute-in-memory (CIM) technology, which performs calculations within or near memory, overcoming the limitations of traditional architectures that require data transfer between separate memory and processor units.
Professor Kwon Ji-min stated, "Just as it is important to build a tall building stably by increasing the number of floors, the key to three-dimensional semiconductors is to ensure stable operation while stacking them high. This technology is expected to accelerate the development of next-generation memory semiconductors that increase AI computation speed while reducing power consumption."
Researcher Koo Hyun-ho from KAIST served as the first author, with Dr. Lee Yong-woo, Dr. Jeong Hak-soon, and Professor Kwon Ji-min as corresponding authors. Researchers from UNIST, Yonsei University, the Korea Institute of Chemical Technology, Seoul National University of Science and Technology, and Seoul National University also participated in the collaborative research.
The research findings were published on May 20 in the international journal 'Advanced Functional Materials' and were selected as a cover paper due to their academic significance and originality.
* This article has been translated by AI.
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