The competition for performance in AI semiconductors is expanding beyond faster logic and high-bandwidth memory (HBM) to how closely these components are interconnected. As AI computational capabilities increase, the speed of data storage and transfer has emerged as a limiting factor, known as the 'memory wall.' In South Korea's semiconductor industry, which leads in HBM, advanced packaging capabilities that connect logic and memory are becoming crucial for next-generation competitiveness.
During a media briefing on DRAM and advanced packaging for the AI era held on August 31 at the Oakwood Premier Coex Center in Seoul, Mukund Srinivasan, vice president of Applied Materials, identified power efficiency as a key challenge for AI semiconductors. He categorized AI semiconductors into logic, memory, and the packaging that connects them, stating, "In packaging, logic and memory must be placed very close to each other."
As logic evolves into three-dimensional structures like gate-all-around (GAA) and memory advances to HBM with vertically stacked DRAM, packaging is also advancing from 2.5D to 3D structures. Srinivasan highlighted speed, latency, and bandwidth as essential requirements for next-generation DRAM. He explained that increasing input/output density and reducing the distance between logic and memory can lower the time and power needed for data movement.
HBM stacking technology is evolving in a similar direction. Currently, the predominant method connects DRAM using microbumps, but as the number of layers increases, the spacing between contacts and chips must decrease. Srinivasan noted, "To enhance the power efficiency of HBM while scaling, we need to transition from microbump-based stacking to hybrid bonding." Hybrid bonding is a technology that reduces the spacing between chips, improving thermal efficiency, integration density, latency, and bandwidth.
However, the timeline for the full commercialization of hybrid bonding in HBM remains uncertain. In a Q&A session, Srinivasan acknowledged hybrid bonding as a promising technology for HBM but stated that the specific application timeline is a decision for customers. He anticipated that while new semiconductor technologies require a learning curve, technical challenges will be resolved.
This shift presents new challenges for industry leaders Samsung Electronics and SK Hynix, which dominate the HBM market. Park Kwang-sun, president of Applied Materials Korea, remarked, "Two of the three companies manufacturing advanced memory are in Korea, and this is further enhanced by packaging and advanced logic." He assessed that Korea's strategic importance will continue to grow, adding, "We are discussing how to rapidly develop and apply packaging technology that connects chips."
According to Srinivasan, the approach to technology development is also changing. He noted that advanced logic requires over 2,000 process steps, while memory needs more than 1,200. He emphasized the importance of 'joint optimization,' which focuses on optimizing materials, processes, and measurements together rather than improving individual processes separately.
To facilitate this, Applied Materials is establishing the EPIC Center in Silicon Valley, USA. The goal is to reduce the commercialization timeline by having customers and equipment and materials companies collaborate from initial technology development to mass production. Samsung Electronics and SK Hynix are also participating as funding partners. Park stated that they aim to connect the initial technologies developed at the EPIC Center in the U.S. with a collaboration center being built in Korea to expedite the commercialization of products for domestic customers.
* This article has been translated by AI.
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