Chinese memory semiconductor company CXMT (Changxin Memory Technologies) is set to enter the server memory market with its next-generation DRAM technology. The company aims to expand its focus from consumer electronics to high-performance server memory, challenging the high-value market dominated by Samsung Electronics, SK Hynix, and Micron Technology.
According to a report by the Chinese publication Kechuangban Daily on October 12, CXMT CEO Qiao Kanyu announced at an industry conference on October 10 that the company plans to launch DDR5 RDIMM server memory products utilizing the 4F² (4F squared) DRAM architecture by the end of this year. RDIMM is a hardware buffer that maintains signals from the central processing unit for exactly one clock cycle. The 4F² design technology reduces the area of memory cells, increasing density. This allows for higher storage capacity per chip compared to the currently dominant 6F² structure. Qiao stated that CXMT aims to overcome the technical barriers that have hindered its entry into the server memory market using this technology.
The key technology is the vertical surround gate (VSG) transistor. Industry experts in China estimate that applying the 4F² structure could increase cell density by 30% to 50% compared to existing designs. CXMT has disclosed over 300 patents related to this architecture.
The development of this product is expected to serve as a litmus test for CXMT's technological competitiveness in the server memory market. Tianfeng FastSync Research Institute's director noted in an interview with the Global Times that while the world's top three memory companies are also pursuing the development of 4F² or similar 3D DRAM technologies, they have yet to achieve large-scale commercialization. If CXMT successfully commercializes its product first, it could secure a competitive edge in the next-generation memory market and enhance China's advanced semiconductor supply chain.
Meanwhile, Samsung Electronics plans to commercialize the 4F² architecture in 2028. The company is expected to manufacture memory cells and peripheral circuits on separate wafers and then combine them using hybrid bonding.
* This article has been translated by AI.
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