SEOUL, August 12 (AJP) - The race to build faster artificial intelligence memory is beginning to move beyond simply stacking more DRAM, as chipmakers confront a more fundamental problem: even high-bandwidth memory may not be enough to keep increasingly powerful AI processors fed with data.
For the past several years, competition among memory makers has centered on successive generations of HBM, from HBM3E to HBM4 and HBM4E. SK hynix, Samsung Electronics and Micron have raced to increase bandwidth and capacity while cutting power consumption as demand from AI chipmakers such as Nvidia has surged.
That demand is still accelerating.
Micron Technology estimates the global HBM market will grow from about $35 billion in 2025 to around $100 billion by 2028, representing compound annual growth of roughly 40 percent. The company now expects the market to reach the $100 billion milestone two years earlier than previously forecast.
But as AI models grow larger and inference workloads become more demanding, the industry's focus is broadening from the performance of individual memory chips to how memory, processors, packaging and interconnects are designed together.
At the heart of the shift is the so-called "memory wall" — the widening gap between the speed at which processors can perform calculations and the speed at which data can be supplied to them.
HBM has substantially eased that bottleneck by placing stacks of DRAM close to processors and allowing far larger volumes of data to move in parallel.
It has not eliminated it.
Higher stacks and faster bandwidth bring their own constraints, including heat, power consumption, manufacturing complexity and cost. HBM also consumes a disproportionately large share of DRAM production capacity.
TrendForce estimates HBM will account for about 22 percent of total DRAM wafer input among the world's three major memory suppliers by the end of 2026 while representing only about 9 percent of total DRAM bit supply.
By the end of 2027, those shares are projected to rise to 30 percent and 13 percent, respectively, as larger die sizes and growing demand put greater pressure on production capacity.
The numbers expose a central trade-off. HBM provides enormous bandwidth, but producing it consumes wafer capacity far faster than it expands the industry's overall supply of memory bits.
That makes simply stacking more DRAM an increasingly expensive answer to AI's data problem.
As workloads expand, the challenge is shifting toward how efficiently data can move across an entire computing system — from storage and memory to processors and accelerators — without power consumption, heat or latency overwhelming performance.
Still, industry experts caution against reading the proliferation of new memory concepts as evidence that HBM is about to be displaced.
"There are always many concepts for new forms of memory, but it is extremely difficult for them to go through verification and commercialization and ultimately reach mass production," said Lee Jong-hwan, a professor of system semiconductor engineering at Sangmyung University. "Only a very small number actually make it all the way to mass production."
That is pushing semiconductor companies to explore architectures that extend beyond conventional HBM.
Intel and SoftBank subsidiary SAIMEMORY, for example, are developing Z-Angle Memory, or ZAM, a next-generation stacked DRAM architecture aimed at delivering greater capacity and lower power consumption than current HBM designs.
The project is part of a broader industry effort to rethink the physical relationship between processors and memory rather than relying solely on successive upgrades to existing HBM standards.
Nvidia is also approaching memory increasingly as part of a broader computing architecture.
Its latest Rubin GPU integrates up to 288 gigabytes of HBM4 and delivers up to 22 terabytes per second of memory bandwidth, about 2.8 times that of its Blackwell generation.
But the architecture does not rely on HBM alone. Nvidia is combining faster memory with new memory controllers, tighter compute-memory integration and technologies designed to improve data movement across the system.
The message is increasingly clear: raw bandwidth still matters, but so does everything between the memory cell and the processor.
The shift is unfolding as AI reshapes the wider memory industry.
Counterpoint Research expects server products to account for 56 percent of global memory revenue in 2026, up sharply from 37 percent in 2025, as spending on AI infrastructure shifts demand toward high-performance memory used in data centers.
For Korean memory makers, however, the change does not mean HBM is approaching the end of its growth cycle.
Demand remains strong as Nvidia, AMD and other chipmakers roll out more powerful AI accelerators, while HBM4 and its successors are expected to remain central to AI infrastructure for years.
Rather, the shift suggests that leadership in the next phase of AI memory will require more than producing the fastest or highest-capacity DRAM stack.
SK hynix, currently at the forefront of the HBM market, has already begun positioning itself for that transition.
The company has outlined plans to become what it calls a "full-stack AI memory creator," expanding beyond HBM into AI-focused DRAM and NAND products while working more closely with customers on chip architecture, workloads, power requirements and thermal design.
Its "Memory as a Service," or MaaS, strategy similarly seeks to tailor memory solutions to individual AI systems rather than treating memory as a standardized component supplied after processors have already been designed.
Behind the corporate terminology is a deeper change in the industry's division of labor.
Memory companies historically focused on developing chips to customer specifications and manufacturing them at scale. As the memory wall becomes a larger constraint on AI performance, accelerator designers increasingly need memory, packaging and interconnect technologies optimized alongside the processor itself.
That is pulling memory companies earlier into the system-design process.
Even SK hynix acknowledges that HBM alone is unlikely to be the industry's final answer.
At the RAISE Summit in Paris last month, Kim Ho-sik, vice president responsible for memory system research at SK hynix, said HBM was currently the best available memory technology for alleviating the memory wall but was not the ultimate solution.
His remarks followed criticism from former Intel CEO Pat Gelsinger, who pointed to HBM's thermal and efficiency limitations during a panel discussion and argued that the industry would eventually need a new memory architecture to unlock AI's full potential.
Kim said SK hynix was also studying other approaches to address the bottleneck while stressing that HBM remains the best technology currently available.
The exchange captured the industry's emerging consensus: HBM remains indispensable, but the search for what comes alongside — and eventually beyond — it has already begun.
Lee said, however, that HBM's position is unlikely to be seriously challenged in the near term, pointing to long-term supply agreements between memory makers and their major customers as an important indicator of future demand.
"HBM is likely to remain firmly in place for the time being," Lee said. "The fact that long-term contracts are already in place gives memory makers visibility into how much they will need to produce several years from now and allows them to plan their investments accordingly."
For Samsung Electronics and SK hynix, that could widen the battlefield considerably.
Their competitive advantage was built on the ability to manufacture increasingly dense and sophisticated memory at enormous scale. The AI era is pulling them further upstream, into decisions once dominated by processor and system designers: where memory sits, how it connects and how data flows through the machine.
The next memory war may therefore be decided not by who can stack the most DRAM dies, but by who helps design the AI computer around them.
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